Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)		2015-02-28 11:36:15 +01:00
..
liteeth	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
liteusb	liteusb: move files and modify import to misoclib.com.liteusb	2015-02-28 11:18:00 +01:00
spi	misoclib/com: add spi (only SPIMaster for now)	2015-02-28 09:43:03 +01:00
uart	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00