Florent Kermarrec 5c922320a0 test/test_cpu: Disable NeoRV32 in CI (Seems to be broken with Verilator update).		2023-01-23 08:44:57 +01:00
..
__init__.py	…
test_axi.py	test/test_axi/test_axi_width_converter: Rename and cleanup.	2022-12-08 21:39:08 +01:00
test_axi_lite.py	test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width	2022-07-20 02:44:57 +02:00
test_axi_stream.py	test: Add minimal test_axi_stream test (Just syntax check for now).	2022-09-08 11:53:05 +02:00
test_bitbang.py	…
test_clock.py	cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.	2022-01-25 11:09:15 +01:00
test_code_8b10b.py	soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).	2020-10-21 09:29:21 +02:00
test_cpu.py	test/test_cpu: Disable NeoRV32 in CI (Seems to be broken with Verilator update).	2023-01-23 08:44:57 +01:00
test_csr.py	soc/interconnect/csr: Add optional support fixed CSR mapping.	2022-10-21 14:47:59 +02:00
test_ecc.py	…
test_emif.py	…
test_fifosyncmacro.py	test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow	2022-06-17 16:27:25 +02:00
test_gearbox.py	…
test_hyperbus.py	soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.	2022-03-01 09:11:55 +01:00
test_i2s.py	…
test_icap.py	cores/icap/ICAP: Add Register read capability.	2021-10-04 17:22:57 +02:00
test_led.py	soc/cores/led: Review/Rework #1265.	2022-04-04 15:24:54 +02:00
test_packet.py	test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.	2021-10-23 17:40:41 +02:00
test_prbs.py	…
test_reduce.py	gen/common/Reduce: Add ADD support.	2022-10-28 19:13:27 +02:00
test_spi.py	…
test_spi_opi.py	…
test_stream.py	stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.	2022-09-07 08:59:37 +02:00
test_timer.py	test/test_timer: Update.	2021-05-27 19:37:51 +02:00
test_wishbone.py	soc/interconnect/wishbone: Cleanup in burst cycles support logic	2022-04-12 15:32:29 +02:00