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litex
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Build your hardware, easily!
9 Commits 42 Branches 14 Tags 30 MiB
C 52.7%
Python 43.6%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
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Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
tb/norflash norflash tb: use get_fragment 2011-12-17 15:22:26 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Initial import 2011-12-13 17:33:12 +01:00
build.py uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00