Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete)		2011-12-18 00:29:37 +01:00
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clkfx	clkfx module	2011-12-17 15:00:11 +01:00
lm32	Support the new FHDL syntax	2011-12-16 21:30:22 +01:00
m1reset	Proper reset generation	2011-12-16 22:25:26 +01:00
norflash	Proper reset generation	2011-12-16 22:25:26 +01:00
uart	uart: new design using FHDL and bank (TX only, incomplete)	2011-12-18 00:29:37 +01:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00