361 lines
7.7 KiB
Python
361 lines
7.7 KiB
Python
import math
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from migen.fhdl.std import *
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from migen.fhdl.decorators import ModuleDecorator
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from migen.genlib.resetsync import *
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from migen.genlib.fsm import *
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from migen.genlib.record import *
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from migen.genlib.misc import chooser, optree, Counter, Timeout
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from migen.genlib.cdc import *
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from migen.flow.actor import *
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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from migen.flow.plumbing import Buffer
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from migen.actorlib.fifo import *
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from migen.actorlib.structuring import Pipeline, Converter
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bitrates = {
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"sata_gen3" : 6.0,
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"sata_gen2" : 3.0,
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"sata_gen1" : 1.5,
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}
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frequencies = {
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"sata_gen3" : 150.0,
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"sata_gen2" : 75.0,
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"sata_gen1" : 37.5,
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}
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# PHY / Link Layers
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primitives = {
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"ALIGN" : 0x7B4A4ABC,
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"CONT" : 0X9999AA7C,
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"SYNC" : 0xB5B5957C,
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"R_RDY" : 0x4A4A957C,
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"R_OK" : 0x3535B57C,
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"R_ERR" : 0x5656B57C,
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"R_IP" : 0X5555B57C,
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"X_RDY" : 0x5757B57C,
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"CONT" : 0x9999AA7C,
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"WTRM" : 0x5858B57C,
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"SOF" : 0x3737B57C,
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"EOF" : 0xD5D5B57C,
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"HOLD" : 0xD5D5AA7C,
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"HOLDA" : 0X9595AA7C
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}
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def is_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return True
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return False
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def decode_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return k
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return ""
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def phy_description(dw):
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layout = [
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("data", dw),
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("charisk", dw//8),
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]
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return EndpointDescription(layout, packetized=False)
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def link_description(dw):
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layout = [
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("d", dw),
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("error", 1)
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]
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return EndpointDescription(layout, packetized=True)
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# Transport Layer
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fis_max_dwords = 2048
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fis_types = {
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"REG_H2D": 0x27,
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"REG_D2H": 0x34,
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"DMA_ACTIVATE_D2H": 0x39,
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"PIO_SETUP_D2H": 0x5F,
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"DATA": 0x46
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}
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class FISField():
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def __init__(self, dword, offset, width):
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self.dword = dword
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self.offset = offset
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self.width = width
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fis_reg_h2d_cmd_len = 5
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fis_reg_h2d_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"c": FISField(0, 15, 1),
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"command": FISField(0, 16, 8),
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"features_lsb": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"features_msb": FISField(2, 24, 8),
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"count": FISField(3, 0, 16),
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"icc": FISField(3, 16, 8),
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"control": FISField(3, 24, 8)
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}
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fis_reg_d2h_cmd_len = 5
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fis_reg_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"i": FISField(0, 14, 1),
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"status": FISField(0, 16, 8),
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"count": FISField(3, 0, 16)
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}
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fis_dma_activate_d2h_cmd_len = 1
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fis_dma_activate_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4)
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}
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fis_pio_setup_d2h_cmd_len = 5
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fis_pio_setup_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"d": FISField(0, 13, 1),
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"i": FISField(0, 14, 1),
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"status": FISField(0, 16, 8),
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"lba_msb": FISField(2, 0, 24),
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"count": FISField(3, 0, 16),
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"transfer_count": FISField(4, 0, 16),
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}
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fis_data_cmd_len = 1
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fis_data_layout = {
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"type": FISField(0, 0, 8)
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}
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def transport_tx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("c", 1),
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("command", 8),
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("features", 16),
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("lba", 48),
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("device", 8),
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("count", 16),
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("icc", 8),
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("control", 8),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def transport_rx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("r", 1),
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("d", 1),
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("i", 1),
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("status", 8),
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("errors", 8),
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("lba", 48),
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("device", 8),
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("count", 16),
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("transfer_count", 16),
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("data", dw),
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("error", 1)
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]
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return EndpointDescription(layout, packetized=True)
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# Command Layer
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regs = {
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"WRITE_DMA_EXT" : 0x35,
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"READ_DMA_EXT" : 0x25,
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"IDENTIFY_DEVICE" : 0xEC
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}
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reg_d2h_status = {
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"bsy" : 7,
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"drdy" : 6,
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"df" : 5,
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"se" : 5,
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"dwe" : 4,
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"drq" : 3,
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"ae" : 2,
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"sns" : 1,
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"cc" : 0,
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"err" : 0
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}
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def command_tx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("sector", 48),
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("count", 16),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def command_rx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("last", 1),
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("failed", 1),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def command_rx_cmd_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("last", 1),
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("failed", 1)
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]
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return EndpointDescription(layout, packetized=False)
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def command_rx_data_description(dw):
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layout = [
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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# HDD
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logical_sector_size = 512 # constant since all HDDs use this
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def dwords2sectors(n):
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return math.ceil(n*4/logical_sector_size)
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def sectors2dwords(n):
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return n*logical_sector_size//4
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# Generic modules
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class BufferizeEndpoints(ModuleDecorator):
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def __init__(self, submodule, *args):
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ModuleDecorator.__init__(self, submodule)
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endpoints = get_endpoints(submodule)
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sinks = {}
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sources = {}
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for name, endpoint in endpoints.items():
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if name in args or len(args) == 0:
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if isinstance(endpoint, Sink):
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sinks.update({name : endpoint})
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elif isinstance(endpoint, Source):
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sources.update({name : endpoint})
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# add buffer on sinks
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for name, sink in sinks.items():
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buf = Buffer(sink.description)
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self.submodules += buf
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setattr(self, name, buf.d)
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self.comb += Record.connect(buf.q, sink)
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# add buffer on sources
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for name, source in sources.items():
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buf = Buffer(source.description)
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self.submodules += buf
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self.comb += Record.connect(source, buf.d)
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setattr(self, name, buf.q)
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class EndpointPacketStatus(Module):
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def __init__(self, endpoint):
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self.start = Signal()
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self.done = Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += [
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self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
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self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
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]
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self.sync += \
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If(self.start,
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ongoing.eq(1)
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).Elif(self.done,
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ongoing.eq(0)
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)
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self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
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class PacketBuffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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###
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sink_status = EndpointPacketStatus(self.sink)
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source_status = EndpointPacketStatus(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += [
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cmd_fifo.sink.stb.eq(sink_status.done),
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cmd_fifo.sink.error.eq(sink.error)
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]
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.submodules += data_fifo
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self.comb += [
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Record.connect(self.sink, data_fifo.sink),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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self.source.error.eq(cmd_fifo.source.error),
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If(source_status.done,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
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