Florent Kermarrec 6b24562eea sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)		2015-03-02 10:59:43 +01:00
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flash	flash/spi: make bitbang optional (enabled by default)	2015-03-01 17:15:22 +01:00
litesata	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
sdram	sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)	2015-03-02 10:59:43 +01:00
__init__.py	…