litex/misoclib/mem/sdram
Florent Kermarrec 6b24562eea sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
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bus sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
frontend sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
lasmicon sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
minicon sdram: create test dir and move lasmicon/minicon tests to it 2015-03-02 08:42:55 +01:00
phy sdram: move dfii to phy 2015-03-02 09:08:28 +01:00
test sdram: create test dir and move lasmicon/minicon tests to it 2015-03-02 08:42:55 +01:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00