Florent Kermarrec 3350d33f9c wishbone/Cache: add reverse parameter		2020-01-31 19:31:33 +01:00
..
__init__.py
avalon.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
csr.py	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
csr_bus.py	interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)	2020-01-03 16:36:42 -05:00
csr_eventmanager.py	csr_eventmanager: add name and description args	2019-09-19 17:23:03 +08:00
packet.py	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
stream.py	inteconnect/stream: use PipeValid implementation for Buffer	2020-01-30 09:36:04 +01:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	wishbone/Cache: add reverse parameter	2020-01-31 19:31:33 +01:00
wishbone2csr.py	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)	2019-09-24 17:55:29 +02:00
wishbonebridge.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00