Gabriel Somlo 70eae5cbf9 interconnect/wishbone: increase WB address width to 31 ... This is needed to support memory regions up to 4GB in size (currently limited to 2GB, or 0x8000_0000). FIXME: CI complains about assertions re. axi_lite.address_width in relationship to len(wishbone.adr) and wishbone_adr_shift, which seems to be a problem on the 32bit (vexriscv?) CPU used for CI, but seems to work fine on Rocket. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> foo		2020-08-03 16:11:26 -04:00
..
cores	cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut.	2020-08-03 18:47:17 +02:00
doc	litex: add sphinx_extra_config to generate_docs()	2020-07-24 16:01:54 +08:00
integration	integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram.	2020-07-29 11:10:05 +02:00
interconnect	interconnect/wishbone: increase WB address width to 31	2020-08-03 16:11:26 -04:00
software	liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.	2020-07-28 14:36:49 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00