Gabriel Somlo 70eae5cbf9 interconnect/wishbone: increase WB address width to 31 ... This is needed to support memory regions up to 4GB in size (currently limited to 2GB, or 0x8000_0000). FIXME: CI complains about assertions re. axi_lite.address_width in relationship to len(wishbone.adr) and wishbone_adr_shift, which seems to be a problem on the 32bit (vexriscv?) CPU used for CI, but seems to work fine on Rocket. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> foo		2020-08-03 16:11:26 -04:00
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__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	interconnect/avalon: minor cleanup, remove max on SyncFIFO depth.	2020-07-08 07:53:42 +02:00
axi.py	soc/interconnect/axi: add Wishbone2AXI converter	2020-08-03 12:50:00 -04:00
csr.py	interconnect/csr: add reset_less parameter.	2020-04-06 13:15:08 +02:00
csr_bus.py	interconnect/csr_bus: fix paged access warning	2020-07-20 18:23:09 +02:00
csr_eventmanager.py	csr_eventmanager: add name and description args	2019-09-19 17:23:03 +08:00
packet.py	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
stream.py	interconnect/stream: allow empty description/payload on Endpoint.	2020-07-03 19:29:05 +02:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	interconnect/wishbone: increase WB address width to 31	2020-08-03 16:11:26 -04:00