Sebastien Bourdeauducq 71c2c5813b platforms/mixxeo: remove bank 3 DVI inputs		2013-07-04 19:27:28 +02:00
..
platforms	platforms/mixxeo: remove bank 3 DVI inputs	2013-07-04 19:27:28 +02:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	* generic_platform.py: add a finalize() method	2013-06-27 19:17:02 +02:00
crg.py	Use migen.fhdl.std	2013-05-26 18:07:26 +02:00
generic_platform.py	* generic_platform.py: add a finalize() method	2013-06-27 19:17:02 +02:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	Do not specify period constraints twice	2013-07-04 19:25:29 +02:00