litex/migen
Sebastien Bourdeauducq 72ef4b9683 ioo+pytholite: use new Module API 2013-04-10 23:42:46 +02:00
..
actorlib flow: use Module and new Record APIs 2013-04-10 19:12:42 +02:00
bank New CSR API 2013-03-30 17:28:41 +01:00
bus bus: replace simple bus module with new bidirectional Record 2013-04-01 21:54:21 +02:00
fhdl fhdl/visit: add TransformModule 2013-04-10 23:42:14 +02:00
flow flow: match record fields by position 2013-04-10 21:33:56 +02:00
genlib ioo+pytholite: use new Module API 2013-04-10 23:42:46 +02:00
pytholite ioo+pytholite: use new Module API 2013-04-10 23:42:46 +02:00
sim sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00