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https://github.com/enjoy-digital/litex.git
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7300879b7f
litex
/
misoclib
/
mem
History
Florent Kermarrec
7300879b7f
sdram: move dfii to phy
2015-03-02 09:08:28 +01:00
..
flash
flash/spi: make bitbang optional (enabled by default)
2015-03-01 17:15:22 +01:00
litesata
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
sdram
sdram: move dfii to phy
2015-03-02 09:08:28 +01:00
__init__.py
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00