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625 lines
23 KiB
Python
625 lines
23 KiB
Python
# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
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# This file is Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2013-2014 Robert Jordens <jordens@gmail.com>
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# This file is Copyright (c) 2015-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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from migen import *
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from migen.genlib.misc import timeline
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from migen.fhdl.specials import Tristate
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.spi import SPIMaster
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# SpiFlash Quad/Dual/Single (memory-mapped) --------------------------------------------------------
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_FAST_READ = 0x0b
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_DIOFR = 0xbb
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_QIOFR = 0xeb
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_QIOPP = 0x12
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def _format_cmd(cmd, spi_width):
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"""
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`cmd` is the read instruction. Since everything is transmitted on all
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dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
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width even if dq1-dq3 are don't care during the command phase:
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For example, for N25Q128, 0xeb is the quad i/o fast read, and
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extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
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"""
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c = 2**(8*spi_width)-1
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for b in range(8):
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if not (cmd>>b)%2:
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c &= ~(1<<(b*spi_width))
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return c
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def accumulate_timeline_deltas(seq):
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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return tseq
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class SpiFlashCommon(Module):
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def __init__(self, pads):
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if not hasattr(pads, "clk"):
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self.clk_primitive_needed = True
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self.clk_primitive_registered = False
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pads.clk = Signal()
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self.pads = pads
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def add_clk_primitive(self, device):
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if not hasattr(self, "clk_primitive_needed"):
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return
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# Xilinx 7-series
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if device[:3] == "xc7":
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self.specials += Instance("STARTUPE2",
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i_CLK=0,
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i_GSR=0,
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i_GTS=0,
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i_KEYCLEARB=0,
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i_PACK=0,
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i_USRCCLKO=self.pads.clk,
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i_USRCCLKTS=0,
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i_USRDONEO=1,
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i_USRDONETS=1)
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# Lattice ECP5
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elif device[:4] == "LFE5":
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self.specials += Instance("USRMCLK",
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i_USRMCLKI=self.pads.clk,
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i_USRMCLKTS=0)
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else:
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raise NotImplementedError
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self.clk_primitive_registered = True
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def do_finalize(self):
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if hasattr(self, "clk_primitive_needed"):
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assert self.clk_primitive_registered == True
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class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple SPI flash.
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Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
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Read). Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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spi_width = len(pads.dq)
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assert spi_width >= 2
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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], description="""
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Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
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a result all four wires are ganged together. This means that it is only possible
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to perform half-duplex operations, using this SPI core.
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""")
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self.miso = CSRStatus(description="Incoming value of MISO signal.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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# # #
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cs_n = Signal(reset=1)
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clk = Signal()
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dq_oe = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd_params = {
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4: (_format_cmd(_QIOFR, 4), 4*8),
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2: (_format_cmd(_DIOFR, 2), 2*8),
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1: (_format_cmd(_FAST_READ, 1), 1*8)
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}
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read_cmd, cmd_width = read_cmd_params[spi_width]
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addr_width = 24
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dq = TSTriple(spi_width)
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# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
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self.specials.dq0 = Tristate(pads.dq[0], o=dq.o[0], i=dq.i[0], oe=dq.oe)
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self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
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self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage))
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self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage))
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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dq.o.eq(sr[-spi_width:]),
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dq.oe.eq(dq_oe)
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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# In Dual/Quad mode, no single data pin is consistently
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# an input or output thanks to dual/quad reads, so we need a bit
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# to swap direction of the pins. Aside from this additional bit,
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# bitbang mode is identical for Single/Dual/Quad; dq[0] is mosi
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# and dq[1] is miso, meaning remaining data pin values don't
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# appear in CSR registers.
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If(self.bitbang.storage[3],
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(dq.i[1])
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),
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dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))
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]
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self.comb += [
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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]
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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dqi = Signal(spi_width)
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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dqi.eq(dq.i),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(dqi, sr[:-spi_width]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width//spi_width*div,
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[dq_oe.eq(1), cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width//spi_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width//spi_width)*div,
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[dq_oe.eq(0)]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple memory-mapped SPI flash.
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Supports 1-bit reads. Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for SPI MOSI pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Unused in this design.")
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], description="""Bitbang controls for SPI output.""")
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self.miso = CSRStatus(description="Incoming value of MISO pin.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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# # #
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if hasattr(pads, "wp"):
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self.comb += pads.wp.eq(1)
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if hasattr(pads, "hold"):
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self.comb += pads.hold.eq(1)
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cs_n = Signal(reset=1)
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clk = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd = _FAST_READ
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cmd_width = 8
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addr_width = 24
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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pads.mosi.eq(sr[-1:])
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(pads.miso)
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),
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pads.mosi.eq(self.bitbang.storage[0])
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]
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self.comb += [
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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]
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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miso = Signal()
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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miso.eq(pads.miso),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(miso, sr[:-1]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width*div,
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[cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width)*div,
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[]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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def SpiFlash(pads, *args, **kwargs):
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if hasattr(pads, "mosi"):
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return SpiFlashSingle(pads, *args, **kwargs)
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else:
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return SpiFlashDualQuad(pads, *args, **kwargs)
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# SpiFlash Quad Read/Write (memory-mapped) ---------------------------------------------------------
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class SpiFlashQuadReadWrite(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple SPI flash.
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Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
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Read). Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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spi_width = len(pads.dq)
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max_transfer_size = 8*8
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assert spi_width >= 2
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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], description="""
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Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
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a result all four wires are ganged together. This means that it is only possible
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to perform half-duplex operations, using this SPI core.
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""")
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self.miso = CSRStatus(description="Incoming value of MISO signal.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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queue = self.queue = CSRStatus(4)
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in_len = self.in_len = CSRStorage(4)
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out_len = self.out_len = CSRStorage(4)
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in_left = self.in_left = Signal(max=2**8)
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out_left = self.out_left = Signal(max=2**8)
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self.quad_transfer = Signal(reset=0)
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spi_in = self.spi_in = CSRStorage(max_transfer_size)
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spi_out = self.spi_out = CSRStatus(max_transfer_size)
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cs_n = Signal(reset=1)
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clk = Signal()
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dq_oe = Signal()
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wbone_width = len(bus.dat_r)
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cmd_width = 8
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addr_width = 24
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dq = TSTriple(spi_width)
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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self.specials.dq0 = Tristate(pads.dq[0], o=dq.o[0], i=dq.i[0], oe=dq.oe)
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self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
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if with_bitbang:
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# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
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self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage))
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self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage))
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else:
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self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=dq.oe)
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self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=dq.oe)
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sr = Signal(max(cmd_width, addr_width, wbone_width, max_transfer_size))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr[:wbone_width])
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr[:wbone_width]))
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hw_read_logic_single = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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dq.o.eq(sr[-spi_width:]),
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dq.oe.eq(dq_oe)
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]
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hw_read_logic_quad = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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dq.o.eq(Cat(sr[-1:], Replicate(1, 3))),
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dq.oe.eq(dq_oe)
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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# In Dual/Quad mode, no single data pin is consistently
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# an input or output thanks to dual/quad reads, so we need a bit
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# to swap direction of the pins. Aside from this additional bit,
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# bitbang mode is identical for Single/Dual/Quad; dq[0] is mosi
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# and dq[1] is miso, meaning remaining data pin values don't
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# appear in CSR registers.
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If(self.bitbang.storage[3],
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(dq.i[1])
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),
|
|
dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))
|
|
]
|
|
|
|
self.comb += [
|
|
If(self.bitbang_en.storage,
|
|
bitbang_logic
|
|
).Elif(self.quad_transfer,
|
|
hw_read_logic_single
|
|
).Else(
|
|
hw_read_logic_quad
|
|
)
|
|
]
|
|
|
|
else:
|
|
self.comb += [
|
|
If(self.quad_transfer,
|
|
hw_read_logic_single
|
|
).Else(
|
|
hw_read_logic_quad
|
|
)
|
|
]
|
|
|
|
if div < 2:
|
|
raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
|
|
|
|
# spi is byte-addressed, prefix by zeros
|
|
z = Replicate(0, log2_int(wbone_width//8))
|
|
i = Signal(max=div)
|
|
dqi = Signal(spi_width)
|
|
|
|
# SPI or memmap mode
|
|
self.mode = Signal()
|
|
|
|
self.sync += [
|
|
If(i == div//2 - 1,
|
|
clk.eq(1),
|
|
dqi.eq(dq.i),
|
|
),
|
|
If(i == div - 1,
|
|
i.eq(0),
|
|
clk.eq(0),
|
|
If(self.quad_transfer,
|
|
sr.eq(Cat(dqi, sr[:-spi_width]))
|
|
).Else(
|
|
sr.eq(Cat(dqi[1], sr[:-1]))
|
|
)
|
|
).Else(
|
|
i.eq(i + 1),
|
|
),
|
|
]
|
|
|
|
read_seq = [
|
|
(4*cmd_width//spi_width*div,
|
|
[dq_oe.eq(1), cs_n.eq(0), sr[-cmd_width:].eq(_QIOFR), self.quad_transfer.eq(0)]),
|
|
(addr_width//spi_width*div,
|
|
[sr[-addr_width:].eq(Cat(z, bus.adr)), self.quad_transfer.eq(1)]),
|
|
((1+dummy + wbone_width//spi_width)*div,
|
|
[dq_oe.eq(0)]),
|
|
(1,
|
|
[bus.ack.eq(1), cs_n.eq(1)]),
|
|
(div, # tSHSL!
|
|
[bus.ack.eq(0)]),
|
|
(0,
|
|
[queue.status[0].eq(0)]),
|
|
]
|
|
|
|
|
|
write_seq = [
|
|
(4*cmd_width//spi_width*div,
|
|
[dq_oe.eq(1), cs_n.eq(0), sr[-cmd_width:].eq(_QIOPP), self.quad_transfer.eq(0)]),
|
|
(addr_width//spi_width*div,
|
|
[sr[-addr_width:].eq(Cat(z, bus.adr)), self.quad_transfer.eq(1)]),
|
|
((wbone_width//spi_width)*div,
|
|
[sr[-wbone_width:].eq(reverse_bytes(bus.dat_w))]),
|
|
(1,
|
|
[bus.ack.eq(1), cs_n.eq(1)]),
|
|
(div,
|
|
[bus.ack.eq(0)]),
|
|
(0,
|
|
[queue.status[1].eq(0)]),
|
|
]
|
|
|
|
# prepare spi transfer
|
|
self.sync += If(self.out_len.re & (self.out_len.storage != 0) & self.en_quad.storage[0],
|
|
self.out_left.eq(Cat(1, self.out_len.storage)
|
|
)
|
|
)
|
|
|
|
self.sync += If(self.out_len.re & (self.out_len.storage == 0),
|
|
self.out_left.eq(0)
|
|
)
|
|
self.sync += If(self.out_len.re & (self.out_len.storage != 0) & ~self.en_quad.storage[0],
|
|
self.out_left.eq(Cat(1, Replicate(0, 2), self.out_len.storage))
|
|
)
|
|
self.sync += If(self.in_len.re & (self.in_len.storage != 0) & ~self.en_quad.storage[0],
|
|
[queue.status[2].eq(1),
|
|
self.in_left.eq(Cat(Replicate(0, 3), in_len.storage)),
|
|
self.quad_transfer.eq(0)]
|
|
)
|
|
|
|
# write data to sr
|
|
self.sync += If(queue.status[2] & (i == div - 1) & ~self.en_quad.storage[0],
|
|
sr[-max_transfer_size:].eq(self.spi_in.storage), queue.status[2].eq(0), queue.status[3].eq(1), cs_n.eq(0), dq_oe.eq(1))
|
|
|
|
# count spi to slave transfer cycles
|
|
self.sync += If(queue.status[3] & (self.in_left > 0) & (i == div - 1), self.in_left.eq(self.in_left - 1), dq_oe.eq(1))
|
|
# count spi to master transfer cycles
|
|
self.sync += If(queue.status[3] & (self.in_left < 1) & (self.out_left > 0) & (i == div - 1), self.out_left.eq(self.out_left - 1), dq_oe.eq(0))
|
|
|
|
#end transmision and read data from sr
|
|
self.sync += If(~self.in_len.re & (in_left < 1) & (out_left < 1) & queue.status[3], queue.status[3].eq(0), cs_n.eq(1),
|
|
If(self.out_len.storage == 1, self.spi_out.status.eq(Cat(Replicate(0, 8*7), sr))
|
|
).Elif(self.out_len.storage == 2, self.spi_out.status.eq(Cat(Replicate(0, 8*6), sr))
|
|
).Elif(self.out_len.storage == 3, self.spi_out.status.eq(Cat(Replicate(0, 8*5), sr))
|
|
).Elif(self.out_len.storage == 4, self.spi_out.status.eq(Cat(Replicate(0, 8*4), sr))
|
|
).Elif(self.out_len.storage == 5, self.spi_out.status.eq(Cat(Replicate(0, 8*3), sr))
|
|
).Elif(self.out_len.storage == 6, self.spi_out.status.eq(Cat(Replicate(0, 8*2), sr))
|
|
).Elif(self.out_len.storage == 7, self.spi_out.status.eq(Cat(Replicate(0, 8*1), sr))
|
|
).Else(self.spi_out.status.eq(sr)))
|
|
|
|
# detect mem map access
|
|
self.sync += If(~self.mode & bus.cyc & bus.stb & ~bus.we, queue.status[0].eq(1))
|
|
self.sync += If(~self.mode & bus.cyc & bus.stb & bus.we, queue.status[1].eq(1))
|
|
|
|
self.sync += timeline(queue.status[0] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(read_seq))
|
|
self.sync += timeline(queue.status[1] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(write_seq))
|
|
|
|
# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ----------------------------------------------
|
|
|
|
class S7SPIFlash(Module, AutoCSR):
|
|
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
|
|
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
|
|
self.specials += Instance("STARTUPE2",
|
|
i_CLK=0,
|
|
i_GSR=0,
|
|
i_GTS=0,
|
|
i_KEYCLEARB=0,
|
|
i_PACK=0,
|
|
i_USRCCLKO=spi.pads.clk,
|
|
i_USRCCLKTS=0,
|
|
i_USRDONEO=1,
|
|
i_USRDONETS=1
|
|
)
|
|
if hasattr(pads, "vpp"):
|
|
pads.vpp.reset = 1
|
|
if hasattr(pads, "hold"):
|
|
pads.hold.reset = 1
|
|
if hasattr(pads, "cs_n"):
|
|
self.comb += pads.cs_n.eq(spi.pads.cs_n)
|
|
self.comb += [
|
|
pads.mosi.eq(spi.pads.mosi),
|
|
spi.pads.miso.eq(pads.miso)
|
|
]
|
|
|
|
|
|
# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------
|
|
|
|
class ECP5SPIFlash(Module, AutoCSR):
|
|
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
|
|
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
|
|
self.specials += Instance("USRMCLK",
|
|
i_USRMCLKI = spi.pads.clk,
|
|
i_USRMCLKTS = 0
|
|
)
|
|
if hasattr(pads, "vpp"):
|
|
pads.vpp.reset = 1
|
|
if hasattr(pads, "hold"):
|
|
pads.hold.reset = 1
|
|
if hasattr(pads, "cs_n"):
|
|
self.comb += pads.cs_n.eq(spi.pads.cs_n)
|
|
self.comb += [
|
|
pads.mosi.eq(spi.pads.mosi),
|
|
spi.pads.miso.eq(pads.miso)
|
|
]
|