| .. |
|
cpu
|
microwatt: Add mmu.vhdl
|
2020-06-10 12:30:52 +09:30 |
|
__init__.py
|
litex: reorganize things, first work working version
|
2015-11-07 17:48:55 +01:00 |
|
bitbang.py
|
litex/build/sim: add module for simulating SPD EEPROM
|
2020-05-28 12:10:25 +02:00 |
|
clock.py
|
diamond: quiet warning about missing clkin freq for EHXPLLL
|
2020-05-04 01:10:09 -07:00 |
|
code_8b10b.py
|
cores/code_8b10b: set reset_less to True on datapath signals.
|
2020-04-06 11:35:18 +02:00 |
|
dna.py
|
cores/dna: cleanup and add add_timing_constraints method
|
2020-01-21 14:08:17 +01:00 |
|
ecc.py
|
soc/cores/ecc: improve readibility, uniformize with others cores
|
2019-09-29 16:02:04 +02:00 |
|
emif.py
|
cores: add External Memory Interface (EMIF) Wishbone bridge.
|
2020-04-12 16:34:33 +02:00 |
|
freqmeter.py
|
soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
|
2019-09-29 16:08:39 +02:00 |
|
gpio.py
|
cores/gpio: add CSR descriptions.
|
2020-03-11 12:06:15 +01:00 |
|
i2s.py
|
Extend I2S capabilities
|
2020-05-20 14:31:51 +02:00 |
|
icap.py
|
soc/cores: use reset_less on datapath/configuration CSRStorages.
|
2020-04-06 13:17:14 +02:00 |
|
identifier.py
|
soc/cores: uniformize (continue)
|
2019-09-29 17:04:21 +02:00 |
|
jtag.py
|
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
|
2019-09-06 11:55:41 +02:00 |
|
led.py
|
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
|
2020-05-08 22:13:47 +02:00 |
|
prbs.py
|
soc/cores: uniformize (continue)
|
2019-09-29 17:04:21 +02:00 |
|
pwm.py
|
soc/cores: use reset_less on datapath/configuration CSRStorages.
|
2020-04-06 13:17:14 +02:00 |
|
spi.py
|
soc/cores/spi: add optional aligned mode.
|
2020-04-22 13:15:51 +02:00 |
|
spi_flash.py
|
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
|
2020-05-12 16:51:47 +02:00 |
|
spi_opi.py
|
Fix off-by-one error on almost full condition for prefetch
|
2020-03-24 08:04:35 +01:00 |
|
timer.py
|
uptime: rework and integrate it in Timer to ease software support.
|
2020-05-17 11:05:14 +02:00 |
|
uart.py
|
soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
|
2020-05-27 18:40:45 +02:00 |
|
up5kspram.py
|
cores/up5ksram: optimize bus.adr decoding
|
2019-07-22 07:55:47 +02:00 |
|
usb_fifo.py
|
soc/cores: uniformize (continue)
|
2019-09-29 17:04:21 +02:00 |
|
xadc.py
|
soc/cores: use reset_less on datapath/configuration CSRStorages.
|
2020-04-06 13:17:14 +02:00 |
