Florent Kermarrec 75bb78a413 cores/clock: Add initial Gowin GW1N PLL support. ... For now limited to one output clock and not supporting phase/duty cycle adjustements.		2021-04-30 11:31:04 +02:00
..
build	Lattice: Fix port names in SDR{in/out} Impl	2021-04-25 19:47:30 +02:00
compat	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	cores/clock: Add initial Gowin GW1N PLL support.	2021-04-30 11:31:04 +02:00
tools	tools/litex_json2dts/framebuffer: Use framebuffer_base.	2021-04-27 18:59:54 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00