Karol Gugala 54f729fbc1 Lattice: Fix port names in SDR{in/out} Impl ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>		2021-04-25 19:47:30 +02:00
..
altera	Quartus: handle vh and svh files	2020-12-20 11:53:08 +01:00
gowin	build/gowin: Don't generate IO_LOC is pin name is X.	2021-02-01 13:08:37 +01:00
lattice	Lattice: Fix port names in SDR{in/out} Impl	2021-04-25 19:47:30 +02:00
microsemi	…
sim	gtkwave: fix error when prefix is empty, make treeopen optional	2021-03-23 10:08:06 +01:00
xilinx	Merge remote-tracking branch 'upstream/master'	2021-02-15 09:29:47 -08:00
__init__.py	…
dfu.py	…
generic_platform.py	build/generic_platform: Minor cosmetic cleanups.	2021-03-10 19:21:02 +01:00
generic_programmer.py	…
io.py	…
openfpgaloader.py	Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load	2021-01-30 13:20:30 +01:00
openocd.py	jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode.	2021-02-04 11:44:43 +01:00
tools.py	Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it.	2021-03-24 17:21:13 +01:00