Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
litex/migen/fhdl
History
Sebastien Bourdeauducq ca431fc7c2 fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
..
__init__.py
module.py fhdl/module: support clock domain remapping of submodules 2013-03-22 18:17:54 +01:00
namer.py
specials.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
structure.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
tools.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
tracer.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
verilog.py fhdl/verilog: optionally disable clock domain creation 2013-03-18 18:45:19 +01:00
visit.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00