Sebastien Bourdeauducq 797411c1a9 generic_platform: do not create clock domains during Verilog conversion		2013-03-18 18:44:58 +01:00
..
platforms	altera_quartus, de0nano: add copyright notices	2013-03-15 12:37:25 +01:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	New clock_domain API	2013-03-15 18:46:11 +01:00
crg.py	New clock_domain API	2013-03-15 18:46:11 +01:00
generic_platform.py	generic_platform: do not create clock domains during Verilog conversion	2013-03-18 18:44:58 +01:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	MultiReg: remove idomain	2013-03-15 19:54:25 +01:00