Sebastien Bourdeauducq 79e5f24a65 Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.		2012-11-28 22:49:22 +01:00
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asmicon	Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.	2012-11-28 22:49:22 +01:00
asmiprobe	Add ASMIprobe core	2012-08-04 16:31:24 +02:00
dfii	Remove uses of the RE signal on field registers	2012-10-09 19:08:37 +02:00
framebuffer	framebuffer: use new SingleGenerator	2012-10-09 21:11:26 +02:00
identifier	Clock frequency detection	2012-05-22 13:23:44 +02:00
lm32	Basic support for new clock domain and instance API	2012-09-10 23:47:06 +02:00
m1crg	Define clock domains instead of passing extra clocks as regular signals	2012-09-11 00:21:07 +02:00
minimac3	Remove uses of the RE signal on field registers	2012-10-09 19:08:37 +02:00
norflash	Remove uses of pads, new constraints system	2012-04-02 19:22:17 +02:00
s6ddrphy	Define clock domains instead of passing extra clocks as regular signals	2012-09-11 00:21:07 +02:00
sram	sram: do not use MemoryPort	2012-11-26 19:32:56 +01:00
timer	Add timer	2012-05-21 19:46:04 +02:00
uart	Remove uses of pads, new constraints system	2012-04-02 19:22:17 +02:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00