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litex/migen/actorlib
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Sebastien Bourdeauducq 51bec340ab sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
..
__init__.py actorlib: Wishbone DMA read master (WIP) 2012-01-10 17:10:18 +01:00
dma_asmi.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
dma_wishbone.py Do not use super() 2012-12-18 14:54:33 +01:00
misc.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
sim.py sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
spi.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
structuring.py Do not use super() 2012-12-18 14:54:33 +01:00