Florent Kermarrec da711ad5f1 liteusb: add simple example design with wishbone bridge and software to control it		2015-05-02 18:21:18 +02:00
..
liteeth	liteeth/core/mac: minor cleanup	2015-05-02 16:48:57 +02:00
litepcie	rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)	2015-05-02 17:07:58 +02:00
liteusb	liteusb: add simple example design with wishbone bridge and software to control it	2015-05-02 18:21:18 +02:00
spi
uart	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
__init__.py
gpio.py	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00