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7fa1cd72a8
litex
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migen
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..
actorlib
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
bank
bus
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
fhdl
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
flow
endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)
2015-02-14 03:10:56 -08:00
genlib
sim
test
util
__init__.py