Florent Kermarrec 8280acd3a7 sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core		2015-03-02 12:17:49 +01:00
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__init__.py	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
cpuif.py	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
sdram.py	sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core	2015-03-02 12:17:49 +01:00