litex/litex/soc
2019-10-31 08:52:04 +01:00
..
cores cpu/minverva: give more explicit error message when not able to elaborate cpu 2019-10-31 08:52:04 +01:00
integration Improve the error message on memory region conflict. 2019-10-30 19:32:20 -07:00
interconnect interconnect/wishbone: fix Converter case when buses are identical 2019-10-11 21:49:11 +02:00
software Fix file names for the mor1kx processor. 2019-10-30 13:50:01 -07:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00