.. |
cpu
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cpu/minverva: give more explicit error message when not able to elaborate cpu
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2019-10-31 08:52:04 +01:00 |
__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
bitbang.py
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soc/cores/bitbang: use new CSRField (no functional change)
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2019-09-16 16:56:00 +02:00 |
clock.py
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soc/cores/clocks: improve readibility
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2019-09-29 15:58:22 +02:00 |
code_8b10b.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
dna.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
ecc.py
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soc/cores/ecc: improve readibility, uniformize with others cores
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2019-09-29 16:02:04 +02:00 |
freqmeter.py
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soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
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2019-09-29 16:08:39 +02:00 |
gpio.py
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soc/cores/gpio: uniformize with others cores
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2019-09-29 16:10:44 +02:00 |
hyperbus.py
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soc/core: simplify/cleanup HyperRAM core
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2019-08-16 14:04:58 +02:00 |
icap.py
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soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
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2019-10-18 10:27:37 +02:00 |
identifier.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
jtag.py
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soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
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2019-09-06 11:55:41 +02:00 |
prbs.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
pwm.py
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cores/pwm: remove default CSR reset values.
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2019-07-29 08:38:28 +02:00 |
spi.py
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soc/cores/spi: use new CSRField (no functional change)
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2019-09-16 17:02:55 +02:00 |
spi_flash.py
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spi_flash: document register fields
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2019-09-20 12:42:43 +08:00 |
timer.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
uart.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
up5kspram.py
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cores/up5ksram: optimize bus.adr decoding
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2019-07-22 07:55:47 +02:00 |
usb_fifo.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
xadc.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |