litex/litex/soc/cores
2019-10-31 08:52:04 +01:00
..
cpu cpu/minverva: give more explicit error message when not able to elaborate cpu 2019-10-31 08:52:04 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
bitbang.py soc/cores/bitbang: use new CSRField (no functional change) 2019-09-16 16:56:00 +02:00
clock.py soc/cores/clocks: improve readibility 2019-09-29 15:58:22 +02:00
code_8b10b.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
dna.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
ecc.py soc/cores/ecc: improve readibility, uniformize with others cores 2019-09-29 16:02:04 +02:00
freqmeter.py soc/cores: rename frequency_meter to freqmeter and uniformize with others cores 2019-09-29 16:08:39 +02:00
gpio.py soc/cores/gpio: uniformize with others cores 2019-09-29 16:10:44 +02:00
hyperbus.py soc/core: simplify/cleanup HyperRAM core 2019-08-16 14:04:58 +02:00
icap.py soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 2019-10-18 10:27:37 +02:00
identifier.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
jtag.py soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) 2019-09-06 11:55:41 +02:00
prbs.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
pwm.py cores/pwm: remove default CSR reset values. 2019-07-29 08:38:28 +02:00
spi.py soc/cores/spi: use new CSRField (no functional change) 2019-09-16 17:02:55 +02:00
spi_flash.py spi_flash: document register fields 2019-09-20 12:42:43 +08:00
timer.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
uart.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
up5kspram.py cores/up5ksram: optimize bus.adr decoding 2019-07-22 07:55:47 +02:00
usb_fifo.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
xadc.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00