Joel Stanley 3922359ba1 test: Reinstate microwatt and neorv32 ... They appear to be passing CI again. Signed-off-by: Joel Stanley <joel@jms.id.au>		2023-02-27 17:46:41 +10:30
..
__init__.py	…
test_axi.py	…
test_axi_lite.py	…
test_axi_stream.py	test: Add minimal test_axi_stream test (Just syntax check for now).	2022-09-08 11:53:05 +02:00
test_bitbang.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_clock.py	…
test_code_8b10b.py	soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).	2020-10-21 09:29:21 +02:00
test_cpu.py	…
test_csr.py	soc/interconnect/csr: Add optional support fixed CSR mapping.	2022-10-21 14:47:59 +02:00
test_ecc.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_emif.py	…
test_fifosyncmacro.py	test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow	2022-06-17 16:27:25 +02:00
test_gearbox.py	inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.	2021-03-18 13:47:10 +01:00
test_hyperbus.py	…
test_i2s.py	…
test_icap.py	cores/icap/ICAP: Add Register read capability.	2021-10-04 17:22:57 +02:00
test_led.py	…
test_packet.py	…
test_prbs.py	…
test_reduce.py	gen/common/Reduce: Add ADD support.	2022-10-28 19:13:27 +02:00
test_spi.py	…
test_spi_opi.py	…
test_stream.py	…
test_timer.py	test/test_timer: Update.	2021-05-27 19:37:51 +02:00
test_wishbone.py	soc/interconnect/wishbone: Cleanup in burst cycles support logic	2022-04-12 15:32:29 +02:00