litex/migen
Robert Jordens 86ba9c8bbc migen.fhdl.size: verify fslice for negative values 2013-12-03 21:39:37 +01:00
..
actorlib actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg 2013-11-02 23:21:05 +01:00
bank replace use of __dict__ with dir()/xdir() 2013-11-02 16:03:47 +01:00
bus bus/wishbone/sram: expose memory component 2013-11-24 23:43:14 +01:00
fhdl migen.fhdl.size: verify fslice for negative values 2013-12-03 21:39:37 +01:00
flow flow/isd: update to new APIs 2013-11-20 17:45:09 +01:00
genlib genlib/divider: fix diff computation 2013-12-02 17:56:03 +01:00
pytholite replace use of __dict__ with dir()/xdir() 2013-11-02 16:03:47 +01:00
sim sim: use Simulator as a contextmanager 2013-11-29 23:05:15 +01:00
test migen.fhdl.size: verify fslice for negative values 2013-12-03 21:39:37 +01:00
util migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things 2013-12-03 21:36:33 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00