Robert Jordens 86ba9c8bbc migen.fhdl.size: verify fslice for negative values		2013-12-03 21:39:37 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
decorators.py	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
edif.py	fhdl/edif: adjust for use with mibuild	2013-08-03 10:54:06 +02:00
module.py	migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things	2013-12-03 21:36:33 +01:00
namer.py	replace use of __dict__ with dir()/xdir()	2013-11-02 16:03:47 +01:00
size.py	migen.fhdl.size: verify fslice for negative values	2013-12-03 21:39:37 +01:00
specials.py	specials/Instance: add PreformattedParam	2013-11-25 12:09:51 +01:00
std.py	migen.fhdl.size: add fiter(), fslice(), and freversed()	2013-12-03 21:36:33 +01:00
structure.py	migen.fhdl.structure: have Cat() flat_iteration-ize its arguments	2013-12-03 21:36:33 +01:00
tools.py	migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things	2013-12-03 21:36:33 +01:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	add ternary operator sel ? a : b	2013-08-12 13:15:56 +02:00
visit.py	fhdl: do not export Fragment	2013-07-25 18:52:54 +02:00