Sebastien Bourdeauducq 8bc1620f2d dvisampler: disable EDID when HPD_EN is low		2013-09-13 23:43:28 +02:00
..
__init__.py	dvisampler: support differential input	2013-07-04 19:18:24 +02:00
analysis.py	Use RenameClockDomains decorator instead of add_submodule	2013-07-26 15:42:44 +02:00
chansync.py	Use RenameClockDomains decorator instead of add_submodule	2013-07-26 15:42:44 +02:00
charsync.py	Use migen.fhdl.std	2013-05-22 17:10:13 +02:00
clocking.py	dvisampler: reset PLL at startup	2013-09-08 12:55:26 +02:00
common.py	dvisampler: mostly working, very basic and slightly buggy DMA	2013-05-06 09:58:12 +02:00
datacapture.py	Use migen.fhdl.std	2013-05-22 17:10:13 +02:00
debug.py	Use RenameClockDomains decorator instead of add_submodule	2013-07-26 15:42:44 +02:00
decoding.py	Use migen.fhdl.std	2013-05-22 17:10:13 +02:00
dma.py	Use new FSM API	2013-06-25 22:25:10 +02:00
edid.py	dvisampler: disable EDID when HPD_EN is low	2013-09-13 23:43:28 +02:00
wer.py	Use migen.fhdl.std	2013-05-22 17:10:13 +02:00