Florent Kermarrec 20207c9c32 liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)		2015-03-22 11:11:37 +01:00
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liteeth	litexxx cores: use default baudrate of 115200 for all tests	2015-03-20 12:22:53 +01:00
liteusb	liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)	2015-03-22 11:11:37 +01:00
spi	com/spi: use .format in tb	2015-03-03 10:44:05 +01:00
uart	uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).	2015-03-12 16:57:38 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00