Florent Kermarrec 95cfc444e6 migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method		2015-03-30 11:37:59 +02:00
..
actorlib	move dma_lasmi to MiSoC	2015-03-02 08:23:02 +01:00
bank	bank: support direct mapping of CSRs on Wishbone	2014-11-30 22:28:39 +08:00
bus	move dfi/lasmibus/wishbone2lasmi to MiSoC sdram	2015-02-27 16:54:22 +01:00
fhdl	migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method	2015-03-30 11:37:59 +02:00
flow	endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)	2015-02-14 03:10:56 -08:00
genlib	migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)	2015-03-18 14:41:43 +01:00
sim	migen: create VerilogConvert and EDIFConvert classes and return it with convert functions	2015-03-30 11:37:55 +02:00
test	test_actor: add unittests for SimActor	2015-03-21 10:02:10 +01:00
util	utils/misc: add gcd_multiple function to compute GCD or any number of integers	2013-12-12 17:36:50 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00