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litex/misoclib/tools/litescope/example_designs
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Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py
2015-03-04 23:13:14 +01:00
..
targets liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
test LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
make.py liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00