litex/migen
Florent Kermarrec 3f15699964 revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
..
actorlib global: pep8 (E225) 2015-04-13 21:11:13 +02:00
bank
bus global: more pep8 2015-04-13 21:33:44 +02:00
fhdl revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
flow global: pep8 (E302) 2015-04-13 20:45:35 +02:00
genlib global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
sim global: pep8 (E302) 2015-04-13 20:45:35 +02:00
test global: pep8 (E302) 2015-04-13 20:45:35 +02:00
util global: pep8 (E302) 2015-04-13 20:45:35 +02:00
__init__.py