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a1f7ecc8c5
litex
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misoclib
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example_designs
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Florent Kermarrec
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
..
targets
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
test
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
__init__.py
…
make.py
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00