Sebastien Bourdeauducq a5bd111370 fhdl/verilog: clean up signal classification and support memory descriptions		2012-01-27 16:54:48 +01:00
..
actorlib	New naming system beginning to work	2012-01-16 18:42:55 +01:00
bank	Remove uses of declare_signal	2011-12-18 21:47:48 +01:00
bus	Use meaningful class names	2012-01-20 23:07:32 +01:00
corelogic	Use meaningful class names	2012-01-20 23:07:32 +01:00
fhdl	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00
flow	flow/ala: fix typo for And (thanks Lars)	2012-01-22 00:32:02 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00