Sebastien Bourdeauducq a5bd111370 fhdl/verilog: clean up signal classification and support memory descriptions		2012-01-27 16:54:48 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	namer/trace_back: behave on None code_context	2012-01-20 22:52:50 +01:00
structure.py	fhdl/structure: memory description	2012-01-27 16:53:34 +01:00
tools.py	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00
verilog.py	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00
verilog_mem_behavioral.py	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00