litex/litex
Florent Kermarrec ad11ff39ad targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 11:19:29 +01:00
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boards targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 11:19:29 +01:00
build build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters. 2020-03-04 09:13:26 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes. 2020-03-04 18:33:08 +01:00
tools litex_sim: fix with_uart parameter. 2020-03-03 19:04:18 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00