litex/litex
2021-09-27 16:14:55 +02:00
..
build build/xilinx/common: Fix Ultrascale SDROutput/Input. 2021-09-21 10:30:36 +02:00
compat soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py. 2021-07-29 18:48:03 +02:00
gen gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
soc software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
tools remote/comm_udp: Add padding bytes to Etherbone probe. 2021-09-22 16:52:08 +02:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00