af3d2a29fc
Currently CSR bus assumed that ~we means reading, that created a problem that when for a CSR if reading has side effects and adr parked unintentionally at that CSR, the reading side effect will be triggered. For SoCs, this happened when upstream bus issued a write transaction with wishbone.sel, then on CSR bus it will be translated as adr = addr, we = 0, which will be interpreted as a read to such address, and trigger undesired side effect for such CSR. Such upstream transaction will be generated by our bus width converter. Given that we signal already presents in CSR Interface, the easiest way to handle such situation is to generate re signal at bus bridges and propagate it all the way down to the Interface. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> |
||
|---|---|---|
| .. | ||
| build | ||
| compat | ||
| gen | ||
| soc | ||
| tools | ||
| __init__.py | ||