litex/misoclib
Florent Kermarrec b157031e8a uart/sim: add pty (optional, to use flterm) 2015-03-09 23:29:06 +01:00
..
com uart/sim: add pty (optional, to use flterm) 2015-03-09 23:29:06 +01:00
cpu litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
mem LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
others move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
soc soc: do_exit is now provided by modules 2015-03-09 17:18:42 +01:00
tools LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
video sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
__init__.py rename milkymist-ng to MiSoC 2013-11-09 15:27:32 +01:00