Sebastien Bourdeauducq 6fa30053bf fhdl/verilog: tristate outputs are always wire		2013-03-06 11:30:52 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	fhdl/autofragment: bugfixes + add auto_attr	2013-03-03 17:53:06 +01:00
namer.py	New 'specials' API	2013-02-22 17:56:35 +01:00
specials.py	fhdl/specials: allow setting memory name	2013-02-25 23:14:03 +01:00
structure.py	New 'specials' API	2013-02-22 17:56:35 +01:00
tools.py	fhdl/verilog: insert reset before listing signals	2013-02-27 18:10:04 +01:00
tracer.py	fhdl/namer: better handling of indices	2012-09-09 19:33:55 +02:00
verilog.py	fhdl/verilog: tristate outputs are always wire	2013-03-06 11:30:52 +01:00
visit.py	fhdl: support nested statement lists	2013-01-05 14:18:15 +01:00