Florent Kermarrec bd4d3cd73b uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)		2015-03-01 12:14:34 +01:00
..
liteeth	liteXXX cores: remove Identifier duplication	2015-03-01 11:24:58 +01:00
liteusb	liteXXX cores: update README and doc	2015-02-28 21:40:59 +01:00
spi	misoclib/com: add spi (only SPIMaster for now)	2015-02-28 09:43:03 +01:00
uart	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00