litex/migen
Florent Kermarrec 452c60e0c3 endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations) 2015-02-14 03:10:56 -08:00
..
actorlib endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations) 2015-02-14 03:10:56 -08:00
bank bank: support direct mapping of CSRs on Wishbone 2014-11-30 22:28:39 +08:00
bus Wishbone DownConverter: Fix sel signal 2014-11-26 19:33:12 +08:00
fhdl fhdl/std: add FinalizeError import 2015-01-23 00:23:41 +08:00
flow endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations) 2015-02-14 03:10:56 -08:00
genlib remove crc since each crc is specific. It's probably better to adapt code for each case. 2015-02-14 03:01:12 -08:00
pytholite remove trailing whitespaces 2014-10-17 17:08:46 +08:00
sim remove trailing whitespaces 2014-10-17 17:08:46 +08:00
test test/test_size: fix slice comparison 2014-11-03 12:08:43 +08:00
util utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 17:36:50 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00