Florent Kermarrec be20fbabe4 soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)		2015-03-28 23:35:44 +01:00
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__init__.py	rename sdram mapping to main_ram	2015-03-21 21:01:46 +01:00
cpuif.py	cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)	2015-03-02 16:52:17 +01:00
sdram.py	soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)	2015-03-28 23:35:44 +01:00