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..
com	…
cpu	…
mem	sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)	2015-03-28 16:35:15 +01:00
others	move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)	2015-02-28 11:51:51 +01:00
soc	soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)	2015-03-28 23:35:44 +01:00
tools	…
video	…
__init__.py	…