Sebastien Bourdeauducq fee70e9866 Use Wishbone SRAM component from Migen		2012-12-01 12:59:32 +01:00
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asmicon	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 23:41:51 +01:00
asmiprobe	Add ASMIprobe core	2012-08-04 16:31:24 +02:00
dfii	Remove uses of the RE signal on field registers	2012-10-09 19:08:37 +02:00
framebuffer	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
identifier	Clock frequency detection	2012-05-22 13:23:44 +02:00
lm32	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
m1crg	Define clock domains instead of passing extra clocks as regular signals	2012-09-11 00:21:07 +02:00
minimac3	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
norflash	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
s6ddrphy	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
timer	Add timer	2012-05-21 19:46:04 +02:00
uart	Use new bitwidth/signedness system	2012-11-29 23:38:04 +01:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00