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Build your hardware, easily!
138 Commits 40 Branches 14 Tags 26 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
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Florent Kermarrec c17159754c add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
lib/sata add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
platforms update clock constraints for SATA1 and use sys_clk of 200MHz 2014-12-17 19:24:23 +01:00
sim various fixes and simplifications, SATA1 & SATA2 OK 2014-10-28 02:15:19 +01:00
targets add mode generic CommandGenerator for debug 2014-12-20 16:21:26 +01:00
test add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
Makefile use Vivado programmer instead of IMPACT 2014-12-17 12:07:11 +01:00
README init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00

README 

             _____       _            ____  _     _ _       _ 
            |   __|___  |_|___ _ _   |    \|_|___|_| |_ ___| |
            |   __|   | | | . | | |  |  |  | | . | |  _| .'| |
            |_____|_|_|_| |___|_  |  |____/|_|_  |_|_| |__,|_|
                      |___|   |___|          |___|
 
 	Copyright 2014 / Florent Kermarrec / florent@enjoy-digital.fr
 
                        Kintex-7 SATA PHY for M-Labs
--------------------------------------------------------------------------------

[> Getting started
------------------
1. Obtain MiSoC and follow its "Quick start guide". Set the MSCDIR environment
  variable to the MiSoC directory.

2. Build design:
  make all
  
3. Load design:
  make load

4. Run test:
  make test

[> Cores :
  - UART2Wishbone bridge
  - SATA PHY

[> Contact
E-mail: florent@enjoy-digital.fr