litex/lib/sata
Florent Kermarrec c17159754c add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
..
command add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
link change FIS endianness (seems to be little endian) 2014-12-20 12:58:37 +01:00
phy use new submodules collection to expose more fsm an modules 2014-12-19 22:50:35 +01:00
test add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 2014-12-20 13:26:07 +01:00
transport add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 2014-12-20 13:26:07 +01:00
__init__.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00
bist.py use new submodules collection to expose more fsm an modules 2014-12-19 22:50:35 +01:00
common.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00