litex/lib/sata/test
Florent Kermarrec 9dc6903c55 add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples)
it seems endianness is correct by is only printed in LSB first in Lecroy software
2014-12-20 13:26:07 +01:00
..
Makefile add phy_datapath_tb and start datapath simplification 2014-12-19 16:48:22 +01:00
bist_tb.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00
command_tb.py add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 2014-12-20 13:26:07 +01:00
common.py change FIS endianness (seems to be little endian) 2014-12-20 12:58:37 +01:00
cont_tb.py add cont_tb and rewrite cont 2014-12-19 11:15:01 +01:00
crc.c move test 2014-12-05 17:48:01 +01:00
crc_tb.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00
hdd.py add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 2014-12-20 13:26:07 +01:00
link_tb.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00
phy_datapath_tb.py SATAPHYDatapathRX: use Converter and simplify 2014-12-19 17:27:44 +01:00
scrambler.c move test 2014-12-05 17:48:01 +01:00
scrambler_tb.py use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00